1. Field of the Invention
The present invention relates to memory devices based on phase change materials including chalcogenide materials, and methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change between an amorphous phase and a crystalline phase by application of electrical current at levels suitable for implementation in integrated circuits. The amorphous phase is characterized by higher electrical resistivity than the crystalline phase, which can be readily read to indicate data. These properties have generated interest in using programmable resistive material to form non-volatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline phase is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous phase.
One problem arising in phase change devices involves data retention. Phase change memory cells can suffer a drift in resistance over time, as the active region composition shifts from amorphous to crystalline phase, or vice versa, due to environmental conditions to which the device is exposed. For example, a memory cell in which the active region has been reset to a generally amorphous state may over time develop a distribution of crystalline regions in the active region. If these crystalline regions connect to form a low resistance path through the active region, when the memory cell is read a lower resistance state will be detected and result in a data error. See Gleixner, “Phase Change Memory Reliability,” 22nd NVSMW, 2007.
Another problem with phase change memory cells involves reliability issues arising from the difference in density between the crystalline and amorphous phases. The change in volume that occurs because the transition from the amorphous phase to the crystalline phase causes stress within the memory material and at the interface with electrodes. During operation, repeated set and reset operations can cause formation of voids in the phase change material, which can lead to device failure and limit the cycle endurance of the cell. Also, during manufacturing, high temperature back-end-of-line (BEOL) processes can cause a transition from the as-deposited amorphous phase into the higher density crystalline phase, which can cause voids that result in device failure.
Chalcogenides and other phase change materials can be combined with additives to modify conductivity, transition temperature, melting temperature, and other properties of the material. Combining phase change materials with additives is sometimes referred to as “doping with impurities” or adding “dopants.” The terms “additive,” “dopant” or “impurity” can be used interchangeably in connection with this specification. Representative additives used with chalcogenides include nitrogen, silicon, oxygen, silicon oxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium and titanium oxide. See, for example, U.S. Pat. No. 6,800,504 (metal doping), and U.S. Patent Application Publication No. U.S. 2005/0029502 (nitrogen doping). Research has progressed to provide memory devices that operate with low reset current by adjusting the doping concentration in phase change memory.
U.S. Pat. No. 6,087,674 and its parent U.S. Pat. No. 5,825,046 by Ovshinsky et al., describe forming composite memory material in which phase change material is mixed with a relatively high concentration of dielectric material in order to manage the resistance of the composite memory material. The nature of the composite memory material described in these patents is not clear, because it describes composites as layered structures as well as mixed structures. The dielectric materials described in these patents cover a very broad range.
A number of researchers have investigated the use of silicon oxide doping of chalcogenide material for the purposes of reducing the reset current needed for operation of the memory devices. See Ryu, et al., “SiO2 Incorporation Effects in Ge2Sb2Te5 Films Prepared by Magnetron Sputtering for Phase Change Random Access Memory Devices,” Electrochemical and Solid-State Letters, 9 (8) G259-G261 (2006); Lee et al., “Separate domain formation in Ge2Sb2Te5—SiOx mixed layer,” Appl. Phys. Lett. 89,163503 (2006); Czubatyj et al., “Current Reduction in Ovonic Memory Devices,” E*PCOS06 (2006); and Noh et al., “Modification of Ge2Sb2Te5 by the Addition of SiOx for Improved Operation of Phase Change Random Access Memory,” Mater. Res. Soc. Symp. Proc. Vol. 888 (2006). These references suggest that relatively low concentrations of silicon oxide doping in Ge2Sb2Te5 (GST) result in substantial increases in resistance and corresponding reductions in reset current. The Czubatyj et al. article suggests that the improvement in resistance in a silicon oxide doped GST alloy saturates at about 10 vol % (6.7 at %), and reports that doping concentrations up to 30 vol % silicon oxide had been tested, without providing details. The Lee et al. publication describes a phenomenon at relatively high doping concentrations around 8.4 at %, by which the silicon oxide appears to separate from the GST after high-temperature annealing to form domains of GST surrounded by boundaries that are primarily silicon oxide. Doping with silicon dioxide also results in reduction in grain size in the polycrystalline phase of the material, and improves manufacturability.
Hudgens, U.S. Patent Application Publication No. US 2005/0029502, describes a composite doped GST, where nitrogen or nitrogen and oxygen are alleged to cause reduction in grain size, while a second dopant, such as titanium, is applied in a manner that increases the set programming speed. The second dopant in Hudgens is applied to offset an increase in the time needed for set programming caused by nitrogen doping. However, it is found that gas phase dopants like nitrogen and oxygen, while causing a reduction in grain size in the deposited material, have not been reliable, and result in void formations in the material during use.
Chen et al., U.S. Pat. No. 7,501,648 entitled PHASE CHANGE MATERIALS AND ASSOCIATED MEMORY DEVICES, issued 10 Mar. 2009, describes phase change material doped using nitride compounds to affect transition speeds.
Our co-pending U.S. patent application entitled DIELECTRIC MESH ISOLATED PHASE CHANGE STRUCTURE FOR PHASE CHANGE MEMORY, application Ser. No. 12/286,874, filed 2 Oct. 2008, describes the use of silicon dioxide doping in relatively high concentrations and addresses some of the issues discussed above related to changes in composition of the phase change memory materials.
Although substantial benefits in yield can be achieved using additives, issues such as data retention and reliability still arise. Additionally, the use of additives can adversely impact a variety of memory performance characteristics such as set programming speed and threshold voltage compared to that of undoped phase change material, restricting the use of phase change based memory circuits in certain applications.
It is therefore desirable to provide memory cells addressing the yield, endurance, and data retention issues discussed above.